1. Field of the Invention
The present invention relates to a high voltage device and a method for fabricating the same, and more particularly a high voltage device having a polysilicon region in a trench which is capable of mitigating the disadvantage that a maximum operating voltage is lowered due to a latch-up phenomenon by a parasitic bipolar device in a conventional high voltage device.
2. Description of the Background Art
Compared to a general semiconductor device which has an operating voltage range of about 5V, a high voltage device has an operating voltage range from about 40 to 100V. The high voltage device has a structure similar to that of a MOSFET.
FIG. 1A is a sectional view of a conventional double diffused metal oxide semiconductor (DMOS), which is a high voltage device. As shown, an oxide film 2 and a high voltage P-well 3 is sequentially formed on a substrate 1. A P-type drift region 5 and an N-type drift region 4 are formed on the high voltage P-type well 3. A source region 7 is formed on the P-type drift region 5 and a drain region 6 is formed on the N-type drift region 4. A gate region 9 is formed at an upper portion between the P-type drift region 5 and the N-type drift region 4. A gate oxide film and a source and a drain electrodes are omitted on the drawing.
The N-type drift region 4 and the P-type drift region 5 of the conventional DMOS device are formed by doping the substrate lightly with N and P type impurities, respectively near the source and drain regions much like a lightly doped drains (LDD) of a conventional semiconductor device. Because the drift regions 4 and 5 are lightly doped, bulk resistances (Rb) of the drift regions are high.
The conventional high voltage device as shown in FIG. 1A includes a parasitic bipolar junction transistor (BJT) 10 which is formed by the N-type drift region 4, the P-type drift region 5 and the heavily doped source region (N+) 7. The parasitic BJT 10 degrades the operation of the high voltage device.
When the parasitic BJT 10 operates, a collector current of the BJT 10 rapidly increases at a lower voltage than a breakdown voltage of the high voltage device. This lowers the maximum operating voltage of the high voltage device.
FIG. 1B is a graph showing that the maximum operating voltage of the high voltage device is lowered due to the parasitic BJT 10. FIG. 3 shows an equivalent circuit of the high voltage device including the parasitic BJT 10.
The parasitic BJT 10 operates under the following mechanism. Positive holes generated due to impact ionization in the N-type drift region 4 fail to penetrate a potential barrier of the junction between the N+ source region 7 and the P-type drift-region 5, and instead flows to the P+ bulk region 8 after passing below the N+0 source region 7.
When the positive hole current 12 reaches a certain level, the voltage drops so low as to bias in the forward direction the junction between the N+ source region 7 and the P-type drift region 5 due to the bulk resistance (Rb) and thus operating the parasitic BJT 10.
When the parasitic BJT 10 operates, it goes to a latch-up state in which the collector current is not controlled by the voltage applied to the gate and thus the maximum operating voltage is reduced due to the voltage drop across the bulk resistance Rb of the P-type drift region 5.
FIG. 2 is a sectional view of a second conventional DMOS device in accordance with the conventional art which attempts to mitigate the lowering of the maximum operating voltage range. As shown, to mitigate the lowering of the maximum operating voltage caused by the latch-up phenomenon, the P+ bulk region (8′), next to the N+ source region 7, is formed deep and wide to reach the oxide film 2. This reduces the bulk resistance (Rb) of the P-type drift region 5.
However, the second conventional device also has problems. First, in order to form the deep and wide P+ bulk region 8′, a diffusion process to form the P+ bulk region 8′ must be performed over a long time period. Moreover, the resistance is reduced only in the vicinity of the source region 7. It is impossible to lower the resistance of the P-type drift region near a channel below the gate region.